The present invention relates generally to flash memory devices. More particularly, the invention relates to a flash memory device controlling a common source line (CSL) voltage and a program-verify method.
Semiconductor memory devices may generally be classified as volatile memories (e.g., DRAM and SRAM), and nonvolatile memories (e.g., EEPROM, FRAM, PRAM, and flash memory). Volatile memories lose stored data when applied power is interrupted, but nonvolatile memories retain stored data in the absence of applied power. Within the more general class of non-volatile memories, so-called flash memory enjoys a number of advantages including fast programming speed, low power consumption, large date storage capacity, etc. As a result, flash memory has been adopted for use in a wide range of consumer products requiring data storage.
Flash memory includes a memory cell array storing data. The memory cell array is typically divided or arranged into a plurality of memory blocks. Each memory block commonly include a plurality of data pages, and each page is formed from a plurality of memory cells. Binary (or single-level) memory cells (SLC) act as ON-cells or OFF-cells in relation to a present threshold voltage distribution selected between two possible voltage distribution states. (Multi-level memory cells (MLC) select between three or more possible voltage distribution states). On-cells are defined as memory cells having an erased state, while OFF-cells are programmed. Flash memory generally performs an erase operation on a memory block by memory block basis. In contrast, program and read operations are performed page by page.
Flash memory is configured in a cell string structure. The cell string includes a string selection transistor connected to a string selection line (SSL), memory cells connected to a corresponding plurality of word lines (e.g., WL0˜WL31), and a ground selection transistor connected to a ground selection line (GSL). The string selection transistor is connected to a bit line (BL), and the ground selection transistor is connected to a common source line (CSL).
As noted above, flash memory may incorporate SLC and/or MLC memory cells. The proliferation of threshold voltage distributions required to store multi-level data creates increasingly narrow separation widths between adjacent threshold voltage distributions. In other words, discrimination or read margins are shrinking with an increasing number of possible threshold voltage distributions. It is therefore important to avoid spreading or broadening of one or more threshold voltage distributions.
In order to preserve defined separation widths between adjacent threshold voltage distributions, flash memory should avoid changing the voltage level apparent on the CSL during program-verify and read operations. That is, during the program-verify and read operations, the amount of current flowing through respective memory cells should not be different when said operations are executed in relation to memory cells programmed to the same data state.
However, within conventional flash memory it is quite common for the voltage apparent on the CSL to change due to certain parasitic capacitances associated with the CSL. This is unfortunate since variations in the CSL voltage during program-verify and read operations may cause broadening of one or more threshold voltage distributions for the memory cells.